USART-processor

A universal asynchronous receiver/transmitter is a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with other communication standards such as EIA RS-232.

A UART is usually an individual (or part of an) integrated circuit used for serial communications over a computer or peripheral device serial port. UARTs are now commonly included in microcontrollers. A dual UART or DUART combines two UARTs into a single chip. Many modern ICs now come with a UART that can also communicate synchronously; these devices are called USARTs (universal synchronous/asynchronous receiver/transmitter).

 

Definition

• The 8251A is a programmable serial communication interface chip designed for synchronous and asynchronous serial data communication.
• It supports the serial transmission of data.
• It is packed in a 28 pin DIP. 

The functional block diagram of 825 1A consists five sections. They are:

• Read/Write control logic
• Transmitter
• Receiver
• Data bus buffer
• Modem control.

Read/Write control logic:

• The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according to the control word written into its control register.
• It monitors the data flow.
• This section has three registers and they are control register, status register and data buffer.
• The active low signals RD, WR, CS and C/D(Low) are used for read/write operations with these three registers.
• When C/D(low) is high, the control register is selected for writing control word or reading status word.
• When C/D(low) is low, the data buffer is selected for read/write operation.
• When the reset is high, it forces 8251A into the idle mode.
• The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.

Transmitter section:

• The transmitter section accepts parallel data from CPU and converts them into serial data.
• The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits.
• When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register.
• If buffer register is empty, then TxRDY is goes to high.
• If output register is empty then TxEMPTY goes to high.
• The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART.
• The clock frequency can be 1,16 or 64 times the baud rate.

Receiver Section:

• The receiver section accepts serial data and convert them into parallel data
• The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.
• When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples the line again.
• If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register.
• The CPU reads the parallel data from the buffer register.
• When the input register loads a parallel data to buffer register, the RxRDY line goes high.
• The clock signal RxC (low) controls the rate at which bits are received by the USART.
• During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission.
• During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character.

MODEM Control:

• The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines.

• This unit takes care of handshake signals for MODEM interface.

Transmitting and receiving serial data

The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of the serial communications subsystem of a computer. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes. Serial transmission of digital information (bits) through a single wire or other medium is much more cost effective than parallel transmission through multiple wires. A UART is used to convert the transmitted information between its sequential and parallel form at each end of the link. Each UART contains a shift register which is the fundamental method of conversion between serial and parallel forms.

The UART usually does not directly generate or receive the external signals used between different items of equipment. Typically, separate interface devices are used to convert the logic level signals of the UART to and from the external signaling levels.

Asynchronous receiving and transmitting

In asynchronous transmitting, teletype-style UARTs send a "start" bit, five to eight data bits, least-significant-bit first, an optional "parity" bit, and then one, one and a half, or two "stop" bits. The start bit is the opposite polarity of the data-line's idle state. The stop bit is the data-line's idle state, and provides a delay before the next character can start. (This is called asynchronous start-stop transmission). In mechanical teletypes, the "stop" bit was often stretched to two bit times to give the mechanism more time to finish printing a character. A stretched "stop" bit also helps resynchronization.

The parity bit can either make the number of "one" bits between any start/stop pair odd, or even, or it can be omitted. Odd parity is more reliable because it assures that there will always be at least one data transition, and this permits many UARTs to resynchronize.

In synchronous transmission, the clock data is recovered separately from the data stream and no start/stop bits are used. This improves the efficiency of transmission on suitable channels since more of the bits sent are usable data and not character framing. An asynchronous transmission sends no characters over the interconnection when the transmitting device has nothing to send—only idle stop bits; but a synchronous interface must send "pad" characters to maintain synchronism between the receiver and transmitter. The usual filler is the ASCII "SYN" character. This may be done automatically by the transmitting device.

USART chips have both synchronous and asynchronous modes.

Asynchronous transmission allows data to be transmitted without the sender having to send a clock signal to the receiver. Instead, the sender and receiver must agree on timing parameters in advance and special bits are added to each word which are used to synchronize the sending and receiving units.

The start bit is always a 0 (logic low), which is also called a space. The start bit signals the receiving DTE that a character code is coming. The next five to eight bits, depending on the code set employed, represent the character. In the ASCII code set the eighth data bit may be a parity bit. The next one or two bits are always in the mark (logic high, i.e., '1') condition and called the stop bit(s). They provide a "rest" interval for the receiving DTE so that it may prepare for the next character which may be after the stop bit(s).